this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev.0 2 /j an. 9 9 hyundai semiconductor h y63v16 1 00 a series 64 kx16bit cmos fast s ram preliminary description the hy6 3 v16 1 00 a is a 1,048,576-bit high-speed, sram o rganized as 65,536 words by 16 bits. the hy63v16 1 00 a uses sixteen common input and output lines and has an output enable pin which operates faster than address access time at a read cycle. also it allows that lower and upper byte access by data byte control (/ub, /lb). the device is fabricated using hyundai's advanced cmos process and designed for high-speed circuit technology. it is particular l y well suited for being used in high-density and low power system applications. features single 3.3v 0.3v power supply fully static operation and tri-state output ttl compatible inputs and outputs data byte control - lb : i/o1 ~ i/o8, ub : i/o9 ~ i/o16 low data retention voltage: - 2.0v(min)-l- ver.only center power/ground pin configuration standard pin configuration - 44 pin 400mil soj/tsop-ii product supply speed operation standby current( m a) no. voltage(v) ( ns) current( ma) l hy63v16 1 00 a 3.3 8 240 5 0.5 hy63v16 1 00 a 3.3 10 230 5 0.5 hy63v16 1 00 a 3.3 12 220 5 0.5 pin connection (top view ) block diagram soj/tsop2 pin description pin name pin fun c tion pin name pin fun c tion /cs chip select i/o1~i/o16 data input/output /we write enable a0~a15 address input /oe output enable vcc power(+3.3v) /lb low byte control(i/o1~i/o8) vss ground /ub upper byte control(i/o9~i/o16) n . c no connection a15 a14 / oe / ub / lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 nc a12 a11 a10 a9 nc a13 a0 a1 a2 a3 a4 / cs i/o1 i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 / we a5 a6 a7 a8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 soj/ tsop2 row decoder memory array 512x128x16 sense amp write driver output buffer i/o1 i/o8 i/o9 i/o16 decoder add input buffer a0 a15 / cs / oe / lb / ub / we
hy63 v161 00 a series rev.0 2 / j an .9 9 2 absolute maximum ratings(1) symbol parameter rating unit v in, v out voltage on any pin relative to vss -0.5 to 4.6 v vcc voltage on vcc supply relative to vss -0.5 to 5.5 v commercial 0 to 70 c t a operating temperature industrial -40 to 85 c t stg storage temperature -65 to 150 c p d power dissipation 1.0 w note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. recommended dc operating conditions ( t a =0 c to 70 c) symbol parameter min. type max. unit vcc supply voltage 3.0 3 . 3 3 . 6 v vss ground 0 0 0 v v ih input high voltage 2. 0 - vcc+0. 3(2) v v il input low voltage -0. 3(1) - 0.8 v note 1. v il (min) = - 2 .0v a.c ( pulse width less than 8ns) for i < 20 ma 2. v ih (max) = vcc + 2.0v a.c( pulse width less than 8ns) for i < 20 ma dc electrical characteristics ( vcc = 3 . 3 v 0.3v , t a = 0 c to 70 c , unless otherwise specified. ) symbol parameter test conditions min typ max unit i li input leakage current v ss < v in < v cc -2 - 2 ua i lo output leakage current v ss < v out < v cc , /cs = v ih or / oe = v ih or /we = v il -2 - 2 ua 8ns - - 240 ma /cs = v il , v in = v ih , 1 0 ns - - 230 ma i cc operating current i i/o = 0ma 1 2ns - - 220 ma i sb ttl standby current (ttl inputs) /cs = v ih, v in= v ih or v il min. cycle - - 60 ma cmos standby current /cs < v cc -0.2v, v in > - - 5 ma i sb1 (cmos inputs) v cc -0.2v or v in < 0.2v l - 0.5 ma v ol output low voltage i ol = 8.0ma - - 0.4 v v oh output high voltage i oh = -4.0ma 2.4 - - v note : typical values are at vcc = 3. 3 v, t a = 25 c
hy63 v161 00 a series rev.0 2 / j an .9 9 3 ac characteristics ( vcc = 3 . 3 v 0.3v , t a = 0 c to 70 c , unless otherwise specified. ) 8ns 10 ns 12 ns min max min max min max unit read cycle 1 t rc read cycle time 8 - 10 - 12 - ns 2 taa address access time - 8 - 10 - 1 2 ns 3 t acs chip select access time - 8 - 10 - 1 2 ns 4 toe output enable to output valid - 4 - 5 - 6 ns 5 tba /ub,/lb access time - 4 - 5 - 6 ns 6 t clz chip select to output in low z 3 - 3 - 3 - ns 7 tolz output enable to output in low z 0 - 0 - 0 - ns 8 tblz /ub,/lb enable to low-z output 0 - 0 - 0 - ns 9 tchz chip deselecting to output in high z 0 4 0 5 0 6 n s 10 tohz out disable to output in high z 0 4 0 5 0 6 ns 11 tbhz /ub,/lb disable to high-z output 0 4 0 5 0 6 ns 12 toh output hold from address change 3 - 3 - 3 - ns write cycle 13 twc write cycle time 8 - 10 - 12 - ns 14 tcw chip select to end of write 6 - 7 - 8 - ns 15 t aw address valid to end of write 6 - 7 - 8 - ns 16 tas address set-up time 0 - 0 - 0 - ns 17 twp write pulse width (/oe high) 6 - 7 - 8 - ns 18 twp1 write pulse width (/oe low) 8 - 10 - 12 - ns 19 tbw /ub, /lb valid to end of write 6 - 7 - 8 - ns 20 twr write recovery time 0 - 0 - 0 - ns 21 t whz write to output in high z 0 4 0 5 0 6 ns 22 tdw data to write time overlap 4 - 5 - 6 - ns 23 tdh data hold from write time 0 - 0 - 0 - ns 24 tow output active from end of write 3 - 3 - 3 - ns note : above parameters are also guaranteed at industrial temperature range. parameter symbol #
hy63 v161 00 a series rev.0 2 / j an .9 9 4 ac test conditions ( vcc = 3.3 v 0.3v , t a = 0 c to 70 c , unless otherwise specified. ) parameter value input pulse level 0v to 3v input rise and fall time 3ns input and output timing reference level 1.5v output load see below ac test conditions output load (a) output load (b) ( for tchz, tclz, tohz, tolz, twhz & tow) note : * including jig and scope capacitance capacitance temp = 25 c , f= 1.0mhz symbol parameter condition max. unit cin input capacitance v in = 0v 7 pf c i/o input/output capacitance v i/o = 0v 8 pf note : this parameter is sampled and not 100% tested dout 353 w 5 pf * + 3.3 v dout r l =50 w z o = 50 w v l = 1.5 v
hy63 v161 00 a series rev.0 2 / j an .9 9 5 timing diagram read cycle 1 (note 1) addr oe cs ub,lb data out data valid trc tacs tclz toe tolz(5) taa toh tbhz(5) high-z tba tblz(5) tohz(5) tchz(5) read cycle 2 (note 1,2,4) trc taa data valid previous data toh toh addr data out read cycle 3 (note 1,3,4) cs tacs data valid tclz(5) tchz(5) data out notes: 1. /we is high for the read cycle. 2. device is continuously selected. /cs = v il 3. address valid is prior to or coincident with /cs transition low 4. /oe = v il 5. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested.
hy63 v161 00 a series rev.0 2 / j an .9 9 6 write cycle 1 addr cs data out twc tdw tohz(3,9) we data valid tdh twp(1) tas data in tcw twr(2) tbw tas taw ub,lb write cycle 2 (note 5) tdw twhz we data valid tdh twp tas data in twr tcw taw (6) (7) twhz addr cs data out twc notes: 1. a write occurs during the overlap( twp) of a low /cs and low /we . 2. twr is measured from the earlier of /cs, /lb, /ub, or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs, /lb and /ub low transition occur simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. /oe is continuously low(/oe=v il ) 6. q(data out) is the same phase with the write data of this write cycle. 7. q(data out) is the read data of the next address. 8. if /cs is low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 9. transition is measured +200mv from steady state. this parameter is sampled and not 100% tested.
hy63 v161 00 a series rev.0 2 / j an .9 9 7 functional description i/o pin /cs /we /oe /lb /ub mode i/o1 - i/o8 i/o9 - i/o16 supply current h x x* x x not select high-z high-z isb,isb1 l h h x x l x x h h output disable high-z high-z icc l h dout high-z h l high-z dout l h l l l read dout dout icc l h din high-z h l high-z din l l x l l write din din icc * note : x means don,t care data retention electric charateristic ( t a = 0 c to 70 c ) symbol parameter test condition min typ max unit v dr vcc for data retention /cs > vcc - 0.2v 2 .0 - 3.6 v vcc = 3.0v, /cs > vcc - 0.2v v in > vcc -0.2v or v in < 0.2v - - 0.9 i dr data retention current vcc = 2 .0v, /cs > vcc - 0.2v v in > vcc -0.2v or v in < 0.2v - - 0.7 m a tc dr data retention set-up time 0 - - ns t r recovery time 5 - - ms data retention timing diagram cs vdr cs > vcc-0.2v tcdr tr vss vcc 3.0/2.7v 2.2v data retention mode
hy63 v161 00 a series rev.0 2 / j an .9 9 8 package information 44pin 400mil thin small outline package (t2) 44pin 400mil small outline j-form package (j) #22 #23 #44 #1 0.016(0.4) 0.012(0.3) 0.0315(0.800) bsc 0.0059(0.150) 0.002(0.050) 0.047(1.194) 0.039(0.991) 0.721(18.313) 0.729(18.517) 0.10 max 0.004 max 0.404(10.262) 0.396(10.058) 0.0235(0.597) 0.0160(0.406) 0.0083(0.21) 0.0047(0.120 ) 0~5 unit : inch(mm) 0.462(11.735) 0.470(11.938) 0.026(0.660) 0.032(0.813) 0.395(10.033) 1.121(28.473) 0.030(0.762) 0.368(9.348) 0.380(9.652) 0.436(11.074) 0.444(11.278) 0.138(3.505) 0.016(0.406) 0.020(0.508) 0.050(1.27) bsc. 1.129(28.677) unit : inch(mm) 0.405(10.287) 0.148(3.759) 0.040(1.016)
|
